Custom FPGA core development
Design and implementation of workload-specific RTL modules, datapaths and interface logic for customer boards or FPGA platforms.
Services
Custom FPGA core development for workload-specific acceleration
AccelFury offers FPGA IP implementation, verification and bring-up-oriented engineering support. Scope is defined from the workload, target board, interface assumptions and release criteria, not from unsupported benchmark slogans.
Public service catalog
Service surface
AccelFury keeps service descriptions narrow enough to review technically. The work is about FPGA IP, verification, bring-up and prototype acceleration, not generic “full-stack AI infrastructure.”
Verification and testbench development
Simulation-first verification for FPGA IP, including waveform-oriented unit tests, handshake checks, and release evidence packaging.
Board bring-up and integration review
Constraint review, pinout validation, clocking assumptions, board wrapper design, and fail-closed hardware bring-up planning.
ZK acceleration feasibility study
Research-track FPGA architecture work for proof-system bottlenecks such as MSM, NTT/FFT, Poseidon/Merkle pipelines and memory movement.
Edge AI and DSP prototype work
Prototype FPGA dataflow for quantized inference paths, streaming DSP pipelines and latency-oriented preprocessing blocks.
Commercial license and support
Commercial licensing for proprietary use of published AccelFury IP and paid support for integration, review and release readiness.
Working model
Inputs, deliverables and scope limits
Early scoping is most effective when the board, interface, timing target and verification expectations are stated up front.
Typical inputs
Useful first-contact material for a serious review:
- Workload description
- Target FPGA or board
- Clocking and interface constraints
- Latency, throughput and power targets
- Verification and delivery requirements
Typical deliverables
Deliverables depend on scope, but public workflow expectations are explicit rather than implied.
- RTL modules
- Integration notes
- Verification plan and testbenches
- Build constraints and handoff checklist
Known limitations
Performance and power depend on the exact FPGA, board, interfaces and workload. Public claims stay provisional until measured.
- Performance guarantees depend on the exact workload, FPGA family and board constraints.
- Public benchmark numbers are not claimed until reproducible measurements are available.
Proof surface
Public proof
The public af-pdm-rx repository shows the working style this service page is describing: portable Verilog, documented interfaces, simulation-first verification, board wrappers, archived release evidence and explicit pending blockers.
Public repo
af-pdm-rx is the current public engineering proof point for AccelFury.
Public docs
Interface, verification, release and board bring-up notes are visible today.
Next step
Request custom FPGA core development
Send the board, workload, interface assumptions, expected timing and verification scope. If a commercial license or NDA is needed, include that in the first message.