{
  "project": "AccelFury",
  "description": "AccelFury publishes portable FPGA IP cores, an open Rust toolchain (af) and evidence-first hardware acceleration work for cryptography, DSP/audio, edge AI and embedded systems.",
  "status": "Public static B2B FPGA/IP platform with structured core catalog and research-track pages",
  "public_surface": {
    "github_organization": "https://github.com/AccelFury",
    "total_public_repos": 4,
    "ip_cores": 1,
    "tooling_repos": 1,
    "template_repos": 1,
    "published_releases": 0,
    "snapshot": "2026-05-23"
  },
  "tooling": [
    {
      "slug": "af",
      "name": "af",
      "description": "Rust CLI for FPGA IP development: manifests, Verilator simulation, Yosys checks, FuseSoC packaging, vendor backend orchestration.",
      "repository": "https://github.com/AccelFury/af",
      "status": "pre-alpha"
    }
  ],
  "templates": [
    {
      "slug": "core-template",
      "name": "core-template",
      "description": "Production-style FPGA IP repository template with af_mod_add modular-addition example, registries, checks and board metadata.",
      "repository": "https://github.com/AccelFury/core-template",
      "status": "template-ready"
    }
  ],
  "core_categories": [
    {
      "id": "audio_signal_processing",
      "label": "Audio & signal processing",
      "domain": "audio",
      "description": "Streaming audio, PDM, PCM, filtering and signal-processing blocks with explicit clocking and verification status."
    },
    {
      "id": "cryptography",
      "label": "Cryptography",
      "domain": "crypto",
      "description": "Cryptographic datapaths and primitives where public claims are tied to specifications, tests and measured evidence."
    },
    {
      "id": "zk_primitives",
      "label": "ZK-friendly primitives",
      "domain": "crypto",
      "description": "Research and prototype work for field arithmetic, hashes, MSM, NTT and related proof-system bottlenecks."
    },
    {
      "id": "memory_streaming",
      "label": "Memory and streaming",
      "domain": "memory",
      "description": "FIFOs, stream adapters, buffering, backpressure handling and data-movement blocks."
    },
    {
      "id": "interfaces_protocols",
      "label": "Interfaces and protocol adapters",
      "domain": "protocol",
      "description": "Board and subsystem adapters for protocol boundaries, handshakes and integration wrappers."
    },
    {
      "id": "bus_bridges",
      "label": "Bus bridges",
      "domain": "bus",
      "description": "Bridges between internal streams, memory-mapped buses and board-local integration boundaries."
    },
    {
      "id": "edge_ai_dsp",
      "label": "Edge AI / DSP",
      "domain": "AI / DSP",
      "description": "Prototype dataflow for quantized inference, preprocessing and latency-sensitive DSP pipelines."
    },
    {
      "id": "verification_debug",
      "label": "Verification utilities",
      "domain": "verification",
      "description": "Testbench helpers, debug wrappers, checkers and evidence packaging utilities."
    },
    {
      "id": "board_support",
      "label": "Board support wrappers",
      "domain": "board support",
      "description": "Board-local wrappers and constraints that remain fail-closed until build and measurement evidence exist."
    },
    {
      "id": "other",
      "label": "Other documented IP",
      "domain": "other",
      "description": "Reserved for documented cores that do not fit an existing category. It should not be used to hide unclear status."
    }
  ],
  "services": [
    {
      "slug": "custom-fpga-ip-development",
      "title": "Custom FPGA IP development",
      "description": "Specification, RTL implementation, verification and integration support for workload-specific FPGA/IP cores.",
      "status": "Available for technical review",
      "url": "https://accelfury.com/services/custom-fpga-ip-development"
    },
    {
      "slug": "fpga-acceleration-prototyping",
      "title": "FPGA acceleration feasibility review and prototyping",
      "description": "Workload analysis, architecture options, resource estimates, risk review and prototype planning for hardware acceleration projects.",
      "status": "Available for technical review",
      "url": "https://accelfury.com/services/fpga-acceleration-prototyping"
    },
    {
      "slug": "cryptography-zk-acceleration-rd",
      "title": "Cryptography/ZK acceleration R&D",
      "description": "Research-track architecture review and prototype planning for NTT, MSM, hash pipelines and related proof-system bottlenecks.",
      "status": "Research / prototype",
      "url": "https://accelfury.com/services/cryptography-zk-acceleration-rd"
    },
    {
      "slug": "edge-ai-dsp-pipeline-prototyping",
      "title": "Edge AI / DSP pipeline prototyping",
      "description": "Prototype FPGA dataflow for quantized inference paths, streaming DSP pipelines and latency-oriented preprocessing blocks.",
      "status": "Research / prototype",
      "url": "https://accelfury.com/services/edge-ai-dsp-pipeline-prototyping"
    },
    {
      "slug": "commercial-licensing-support",
      "title": "Commercial licensing and support",
      "description": "Commercial licensing discussions and paid support for integration, documentation, priority fixes and release-readiness review.",
      "status": "Available by direct request",
      "url": "https://accelfury.com/services/commercial-licensing-support"
    }
  ],
  "public_assets": [
    {
      "type": "core_catalog",
      "title": "Structured IP core catalog",
      "url": "https://accelfury.com/ip-cores",
      "data_url": "https://accelfury.com/data/cores.json"
    },
    {
      "type": "engineering_notes",
      "title": "Engineering notes",
      "url": "https://accelfury.com/engineering-notes"
    }
  ],
  "docs": [
    "https://accelfury.com/docs",
    "https://accelfury.com/docs/ip-cores",
    "https://accelfury.com/docs/ip-cores.md",
    "https://accelfury.com/docs/services.md",
    "https://accelfury.com/docs/licensing.md",
    "https://accelfury.com/docs/claims-policy.md"
  ],
  "contact": {
    "page": "https://accelfury.com/contact",
    "email": "mail@accelfury.com",
    "workflow": "Static intake form with email-client fallback"
  },
  "claims_policy": {
    "preferredDescription": "AccelFury publishes portable FPGA IP cores, the open af Rust toolchain and evidence-first hardware acceleration work for cryptography, DSP/audio, edge AI and embedded systems.",
    "verifiedFacts": [
      "AccelFury maintains 4 public repositories at github.com/AccelFury (af, af-pdm-rx, core-template, .github).",
      "AccelFury publishes a structured public IP core catalog with 1 true IP core today.",
      "core-template is a public template repository, not a production IP core catalog entry.",
      "Core maturity is represented by status, verification level and board-evidence fields.",
      "The public contact email is mail@accelfury.com."
    ],
    "doNotClaim": [
      "Guaranteed 5x speedup",
      "Guaranteed 60% power reduction",
      "Public production ZK API",
      "Named customers",
      "Named investors",
      "Published release artifacts (no GitHub releases or tags exist yet)",
      "Board-ready or production-ready validation without public evidence"
    ],
    "useWhenUnknown": [
      "Prototype",
      "Research",
      "Planned",
      "Private beta",
      "Not publicly available yet",
      "Benchmark pending",
      "Specification in progress",
      "Contact for technical review"
    ]
  },
  "last_updated": "2026-05-23"
}