{ "project": "AccelFury", "description": "AccelFury develops hardware IP and tools for specialized compute. Our engineering work focuses on FPGA.", "status": "Public static hardware acceleration website with IP and tooling records, scoped engineering and research pages", "positioning": { "category": "Hardware acceleration company", "portability": { "title": "Reusable logic. Target-specific integration.", "principle": "Keep component logic separate from the interfaces, constraints and tools of each target.", "scope": "Support is established for each component version and target through its build and test results." }, "currentTechnology": "FPGA is our current foundation. Additional implementation targets are a development direction." }, "core_categories": [ { "id": "audio_signal_processing", "label": "Audio & signal processing", "domain": "audio", "description": "Streaming audio, PDM, PCM, filtering and signal-processing blocks with explicit clocking and verification status." }, { "id": "cryptography", "label": "Cryptography", "domain": "crypto", "description": "Cryptographic datapaths and primitives where public claims are tied to specifications, tests and measured evidence." }, { "id": "zk_primitives", "label": "ZK-friendly primitives", "domain": "crypto", "description": "Research and prototype work for field arithmetic, hashes, MSM, NTT and related proof-system bottlenecks." }, { "id": "memory_streaming", "label": "Memory and streaming", "domain": "memory", "description": "FIFOs, stream adapters, buffering, backpressure handling and data-movement blocks." }, { "id": "interfaces_protocols", "label": "Interfaces and protocol adapters", "domain": "protocol", "description": "Board and subsystem adapters for protocol boundaries, handshakes and integration wrappers." }, { "id": "bus_bridges", "label": "Bus bridges", "domain": "bus", "description": "Bridges between internal streams, memory-mapped buses and board-local integration boundaries." }, { "id": "edge_ai_dsp", "label": "Edge AI / DSP", "domain": "AI / DSP", "description": "Prototype dataflow for quantized inference, preprocessing and latency-sensitive DSP pipelines." }, { "id": "verification_debug", "label": "Verification utilities", "domain": "verification", "description": "Testbench helpers, debug wrappers, checkers and evidence packaging utilities." }, { "id": "board_support", "label": "Board support wrappers", "domain": "board support", "description": "Board-local wrappers and constraints that remain fail-closed until build and measurement evidence exist." }, { "id": "other", "label": "Other documented IP", "domain": "other", "description": "Reserved for documented cores that do not fit an existing category. It should not be used to hide unclear status." } ], "services": [ { "slug": "custom-fpga-ip-development", "title": "Custom FPGA IP development", "description": "Develop a component for your system, with RTL, simulation tests and integration documentation.", "status": "Available for technical review", "scope": "Design the RTL, interfaces and integration wrapper for the function your system needs.", "acceptanceCriteria": "Interface behaviour and agreed simulation tests pass for the specified configuration. Hardware measurements are included only when scoped.", "commercialModel": "Delivery, licensing and support terms are agreed for the project.", "url": "https://accelfury.com/services/custom-fpga-ip-development/" }, { "slug": "fpga-acceleration-prototyping", "title": "FPGA feasibility and prototyping", "description": "Assess whether a workload fits FPGA acceleration before committing to implementation.", "status": "Available for technical review", "scope": "Compare architecture options, resource estimates and implementation risks. RTL prototyping is a separately agreed deliverable.", "acceptanceCriteria": "The report answers the agreed feasibility questions and records assumptions, estimates, risks and a validation plan.", "commercialModel": "Delivery, licensing and support terms are agreed for the project.", "url": "https://accelfury.com/services/fpga-acceleration-prototyping/" }, { "slug": "cryptography-zk-acceleration-rd", "title": "Zero-knowledge architecture study", "description": "Evaluate arithmetic and memory bottlenecks in proof systems, then define a prototype.", "status": "Research / prototype", "scope": "Select a proof-system bottleneck and compare arithmetic, memory and dataflow options.", "acceptanceCriteria": "The study documents the selected primitive, architecture options, resource estimates and proposed measurements.", "commercialModel": "Delivery, licensing and support terms are agreed for the project.", "url": "https://accelfury.com/services/cryptography-zk-acceleration-rd/" }, { "slug": "edge-ai-dsp-pipeline-prototyping", "title": "Edge AI / DSP pipeline prototyping", "description": "Evaluate FPGA data paths for sensor preprocessing, streaming DSP and selected inference operators.", "status": "Research / prototype", "scope": "Evaluate an operator set or DSP chain against precision, bandwidth and board constraints.", "acceptanceCriteria": "The deliverable records the dataflow, quantization assumptions, latency estimate and target constraints. Prototype RTL requires a separate agreed scope.", "commercialModel": "Delivery, licensing and support terms are agreed for the project.", "url": "https://accelfury.com/services/edge-ai-dsp-pipeline-prototyping/" }, { "slug": "commercial-licensing-support", "title": "Commercial licensing and support", "description": "Agree usage rights and integration support for an existing component.", "status": "Available by direct request", "scope": "Review rights and support for an existing component. New component development is a separate engagement.", "acceptanceCriteria": "The agreement identifies the component, permitted use, delivery terms and support responsibilities.", "commercialModel": "Delivery, licensing and support terms are agreed for the project.", "url": "https://accelfury.com/services/commercial-licensing-support/" } ], "public_assets": [ { "type": "core_catalog", "title": "Structured IP core catalog", "url": "https://accelfury.com/ip-cores/", "data_url": "https://accelfury.com/data/cores.json" }, { "type": "engineering_notes", "title": "Engineering notes", "url": "https://accelfury.com/engineering-notes/" } ], "docs": [ "https://accelfury.com/docs/", "https://accelfury.com/docs/ip-cores/", "https://accelfury.com/docs/api/", "https://accelfury.com/docs/ip-cores.md", "https://accelfury.com/docs/services.md", "https://accelfury.com/docs/licensing.md", "https://accelfury.com/docs/claims-policy.md" ], "contact": { "page": "https://accelfury.com/contact/", "email": "mail@accelfury.com", "workflow": "Static intake form with email-client fallback" }, "claims_policy": { "preferredDescription": "AccelFury develops hardware IP and tools for specialized compute. Our engineering work focuses on FPGA.", "verifiedFacts": [ "AccelFury has a public GitHub organization.", "AccelFury publishes a structured public IP core catalog.", "Lifecycle, access and scoped verification records are separate fields.", "The public site contact email is mail@accelfury.com." ], "doNotClaim": [ "Guaranteed 5x speedup", "Guaranteed 60% power reduction", "Public production ZK API", "Named customers", "Named investors", "Board-ready or production-ready validation without public evidence" ], "useWhenUnknown": [ "Unknown means unconfirmed, not private or unavailable.", "Do not infer lifecycle, availability or a delivery process from missing data." ] }, "last_updated": "2026-10-10", "schemaVersion": 2, "messaging": { "category": "Hardware acceleration company", "descriptor": "Reusable IP and development tools for specialized compute.", "tagline": "Hardware IP and tools for specialized compute.", "oneLiner": "AccelFury develops hardware IP and tools for specialized compute. Our engineering work focuses on FPGA.", "toolName": "FPGA CLI", "home": { "title": "AccelFury | Hardware Acceleration & Specialized Compute", "description": "Hardware IP, FPGA development tools and engineering services. Explore components, assess an acceleration project or discuss custom development with AccelFury.", "eyebrow": "Hardware acceleration", "h1": "Hardware IP and development tools.", "summary": "We develop FPGA components and help hardware teams design, verify and integrate them." }, "socialDescriptor": "Hardware acceleration ยท Specialized compute", "portability": { "title": "Reusable logic. Target-specific integration.", "principle": "Keep component logic separate from the interfaces, constraints and tools of each target.", "scope": "Support is established for each component version and target through its build and test results." }, "foundation": "FPGA is our current foundation. Additional implementation targets are a development direction.", "vision": "We focus on reusable components for specialized compute, with FPGA as our current implementation technology.", "enterprise": "Agree the technical work, delivery terms and responsibilities before a project begins." }, "products": [ { "id": "af-pdm-rx", "kind": "ip", "lifecycle": "prototype", "sourceAccess": "unknown", "distributionAccess": "unknown", "licenseSummary": "AccelFury Source Available License v1.0. Closed-source or proprietary use requires a separate commercial license.", "licenseUrl": "/legal/licensing/", "accessCheckedAt": "2026-10-10", "accessCheckResult": "not_publicly_resolved", "scope": "Based on the site record dated 2026-05-01. Component revision, test configuration and primary reports are unconfirmed; these results have not been independently repeated.", "limitations": [ "Raw PDM only: no PDM-to-PCM conversion, no CIC/FIR and no audio processing.", "The earlier board-build-ready label does not establish functional hardware qualification.", "Measured PDM clock, GPIO loopback and microphone results are unconfirmed.", "A board wrapper does not establish functional hardware support." ], "lastContentReviewedAt": "2026-10-10", "status": "prototype", "verificationLevel": "reported_simulation", "publicReleaseStatus": "Historical board-build-ready label; qualification unknown", "slug": "af-pdm-rx", "name": "af-pdm-rx", "shortDescription": "Verilog-2001 raw PDM receiver IP core for FPGA audio pipelines.", "longDescription": "af-pdm-rx generates a microphone clock, samples one or more raw 1-bit PDM input lanes, packs accepted bits into fixed-width words and exposes a valid/ready stream for downstream FPGA logic.", "category": "audio_signal_processing", "tags": [ "pdm", "audio", "fpga", "verilog", "streaming", "valid-ready" ], "domain": "audio", "license": "AccelFury Source Available License v1.0. Closed-source or proprietary use requires a separate commercial license.", "commercialSupport": true, "lastUpdated": "2026-04-30", "supportedBoards": [ { "name": "Sipeed Tang Primer 20K Dock", "family": "Gowin GW2A", "status": "reported_build", "notes": "Reported wrapper, build and JTAG programming. Functional PDM measurements unconfirmed." }, { "name": "Sipeed Tang Nano 20K", "family": "Gowin GW2AR", "status": "wrapper_only", "notes": "Reported wrapper only. Constraints and functional measurements unconfirmed." }, { "name": "Sipeed Tang Mega 138K Dock", "family": "Gowin GW5A", "status": "wrapper_only", "notes": "Reported wrapper only. Constraints and functional measurements unconfirmed." } ], "supportedToolchains": [ { "name": "Icarus Verilog", "status": "reported_simulation", "notes": "Icarus Verilog / vvp simulation path; source summary only." }, { "name": "OSS CAD Suite / Gowin-compatible flow", "status": "reported_build", "notes": "Selected Tang Primer 20K Dock builds; component revision unconfirmed." } ], "interfaces": [ { "name": "valid_ready_stream", "type": "valid/ready", "direction": "output", "signals": "out_valid_o, out_ready_i, out_data_o, out_lane_o, out_slot_o, out_seq_o", "description": "Packed raw PDM words are emitted over a stable valid/ready stream." }, { "name": "pdm_microphone", "type": "PDM", "direction": "external", "signals": "pdm_clk_o, pdm_dat_i", "description": "External microphone clock output and one or more raw PDM data inputs." }, { "name": "control_status", "type": "simple wires", "direction": "mixed", "signals": "enable_i, clear_i, overflow_o, stat_bits_o, stat_words_o, stat_drops_o", "description": "Control and status wires for enable, synchronous clear, overflow and counters." } ], "parameters": [ [ "LANES", "1", "Number of PDM data pins." ], [ "SLOTS_PER_LANE", "1", "One microphone per line or phase-separated slots." ], [ "WORD_BITS", "64", "Packed raw PDM word width." ], [ "FIFO_ADDR_BITS", "4", "FIFO depth is 2 ** FIFO_ADDR_BITS." ], [ "HALF_PERIOD_CYCLES", "8", "clk_i cycles per half PDM clock period." ], [ "SAMPLE_DELAY_CYCLES", "4", "Delay from PDM clock transition to sample enable." ], [ "LANE_ID_BITS", "1", "Width of out_lane_o; set manually for LANES > 2." ], [ "SEQ_BITS", "32", "Width of output sequence counter." ] ], "ports": [ [ "clk_i", "input", "Only internal logic clock." ], [ "rst_ni", "input", "Asynchronous active-low reset." ], [ "enable_i", "input", "Enables PDM clocking and capture." ], [ "clear_i", "input", "Synchronous one-cycle clear for counters, FIFO, packer and sequence state." ], [ "pdm_clk_o", "output", "External PDM microphone clock." ], [ "pdm_dat_i", "input", "Raw PDM data lines." ], [ "out_valid_o", "output", "Packed word is available." ], [ "out_ready_i", "input", "Downstream accepts the current word." ], [ "out_data_o", "output", "Packed raw PDM bits." ], [ "out_lane_o", "output", "Lane ID for the word." ], [ "out_slot_o", "output", "Slot ID for the word." ], [ "out_seq_o", "output", "Sequence value for the current output word." ], [ "overflow_o", "output", "Sticky overflow/drop indicator until reset or clear_i." ], [ "stat_bits_o", "output", "Count of raw bits accepted by the packer." ], [ "stat_words_o", "output", "Count of output handshakes." ], [ "stat_drops_o", "output", "Count of completed words dropped because FIFO was full." ] ], "clocks": [ { "name": "clk_i", "role": "single internal clock domain", "notes": "All internal state is clocked by clk_i." }, { "name": "pdm_clk_o", "role": "external microphone clock output", "notes": "pdm_clk_o is generated for the microphone and is not used as an internal logic clock." } ], "resets": [ { "name": "rst_ni", "polarity": "active-low", "type": "asynchronous", "notes": "Primary reset for all state." }, { "name": "clear_i", "polarity": "active-high", "type": "synchronous one-cycle clear", "notes": "Clears counters, FIFO, packer and sequence state." } ], "resourceUsage": [], "benchmarks": [ { "name": "Public speed/power benchmark", "status": "benchmark_pending", "notes": "No public speedup or power-ratio benchmark is claimed. Resource and fmax numbers should be treated as target-dependent until measured." } ], "whatItDoes": [ "Generates a PDM microphone clock.", "Samples one or more raw PDM data lanes.", "Packs raw PDM bits into fixed-width words.", "Emits words through a valid/ready stream." ], "whatItDoesNotDo": [ "Does not convert PDM to PCM.", "Does not include CIC, FIR or audio filtering." ], "typicalUseCases": [ "Raw microphone capture experiments.", "FPGA audio front-end prototypes.", "Integration test source for streaming and backpressure paths." ], "integration": { "topLevelWrapper": "af_pdm_rx", "connectionNotes": "Connect clk_i, rst_ni, enable_i, clear_i, PDM pins and downstream valid/ready signals. Keep board-local PLLs and constraints outside the reusable RTL core.", "timingAssumptions": "pdm_clk_o frequency = clk_i frequency / (2 * HALF_PERIOD_CYCLES). Use a board-level PLL or external clock selection when an exact PDM rate is required.", "clockDomains": "Single internal clk_i domain. pdm_clk_o is an external output and not an internal clock.", "boardConstraints": "Check board pins, I/O voltages and clocks before building or programming." }, "publicFacts": [ "The documented Verilog-2001 core uses default_nettype none; portability requires target-specific checks.", "Single internal clock domain clocked by clk_i.", "Raw bit packing into a valid/ready stream.", "Tang Primer 20K Dock is the first documented hardware target." ], "aiSummary": { "facts": [ "af-pdm-rx is an AccelFury Verilog raw PDM receiver IP core; source and package access are unknown.", "Simulation results are reported by the historical site record; primary reports have not been reviewed.", "The historical board-build-ready label does not establish functional hardware qualification." ], "doNotOverclaim": [ "Do not claim PDM-to-PCM conversion.", "Do not claim production readiness.", "Do not claim measured board validation until the pending evidence is public." ] }, "schemaVersion": 2, "pageUrl": "/ip-cores/af-pdm-rx/", "requestUrl": "/contact/?request=ip-evaluation&product=af-pdm-rx&source=product", "verification": [ { "kind": "simulation", "result": "passed", "sourceState": "reported", "scope": "Based on the site record dated 2026-05-01. Component revision, test configuration and primary reports are unconfirmed; these results have not been independently repeated.", "checkedAt": null, "notCheckedReason": "Report and component revision unconfirmed.", "evidenceRefs": [ { "access": "public", "version": "website source dad5cf5bde00f4921bd64d079fa9ce672655ed48", "description": "The source summary reports 13 Icarus test targets and selected Tang Primer 20K Dock builds and JTAG programming. It is not a primary test report.", "locator": "/docs/verification-status/#historical-pdm" } ] }, { "kind": "synthesis", "result": "unknown", "sourceState": "none", "scope": "Based on the site record dated 2026-05-01. Component revision, test configuration and primary reports are unconfirmed; these results have not been independently repeated.", "checkedAt": null, "notCheckedReason": "Report and component revision unconfirmed.", "evidenceRefs": [] }, { "kind": "implementation", "result": "passed", "sourceState": "reported", "scope": "Based on the site record dated 2026-05-01. Component revision, test configuration and primary reports are unconfirmed; these results have not been independently repeated.", "checkedAt": null, "notCheckedReason": "Report and component revision unconfirmed.", "evidenceRefs": [ { "access": "public", "version": "website source dad5cf5bde00f4921bd64d079fa9ce672655ed48", "description": "The source summary reports 13 Icarus test targets and selected Tang Primer 20K Dock builds and JTAG programming. It is not a primary test report.", "locator": "/docs/verification-status/#historical-pdm" } ] }, { "kind": "programming", "result": "passed", "sourceState": "reported", "scope": "Based on the site record dated 2026-05-01. Component revision, test configuration and primary reports are unconfirmed; these results have not been independently repeated.", "checkedAt": null, "notCheckedReason": "Report and component revision unconfirmed.", "evidenceRefs": [ { "access": "public", "version": "website source dad5cf5bde00f4921bd64d079fa9ce672655ed48", "description": "The source summary reports 13 Icarus test targets and selected Tang Primer 20K Dock builds and JTAG programming. It is not a primary test report.", "locator": "/docs/verification-status/#historical-pdm" } ] }, { "kind": "hardware_functional", "result": "unknown", "sourceState": "none", "scope": "Based on the site record dated 2026-05-01. Component revision, test configuration and primary reports are unconfirmed; these results have not been independently repeated.", "checkedAt": null, "notCheckedReason": "Report and component revision unconfirmed.", "evidenceRefs": [] }, { "kind": "formal", "result": "unknown", "sourceState": "none", "scope": "Based on the site record dated 2026-05-01. Component revision, test configuration and primary reports are unconfirmed; these results have not been independently repeated.", "checkedAt": null, "notCheckedReason": "Report and component revision unconfirmed.", "evidenceRefs": [] }, { "kind": "application_acceptance", "result": "unknown", "sourceState": "none", "scope": "Based on the site record dated 2026-05-01. Component revision, test configuration and primary reports are unconfirmed; these results have not been independently repeated.", "checkedAt": null, "notCheckedReason": "Report and component revision unconfirmed.", "evidenceRefs": [] } ] }, { "id": "af", "kind": "toolchain", "lifecycle": "unknown", "sourceAccess": "unknown", "distributionAccess": "unknown", "licenseSummary": "License terms for the current distribution are unconfirmed.", "licenseUrl": "/legal/licensing/", "accessCheckedAt": "2026-10-10", "accessCheckResult": "not_publicly_resolved", "scope": "The current source describes the fpga command; version-specific test results have not been independently reviewed.", "limitations": [ "No current installation command or evaluation package is confirmed.", "Workflow support depends on the supplied version and configuration.", "Integration with a tool does not establish support for every target." ], "lastContentReviewedAt": "2026-10-10", "workflowClaims": [ { "name": "Component checks", "role": "Validate manifests and check RTL structure.", "sourceState": "reported" }, { "name": "Simulation", "role": "Run supported Verilator or Icarus simulation flows.", "sourceState": "reported" }, { "name": "Formal verification", "role": "Run supported SymbiYosys property checks.", "sourceState": "reported" }, { "name": "Reports", "role": "Produce structured results and machine-readable errors.", "sourceState": "reported" } ], "verificationNotCheckedReason": "No current version-specific primary reports have been reviewed.", "slug": "af", "name": "FPGA CLI", "shortDescription": "A command-line tool for FPGA component checks, simulation and formal verification.", "schemaVersion": 2, "pageUrl": "/products/af/", "requestUrl": "/contact/?request=toolchain&product=af&source=product", "verification": [] } ] }