{
  "project": "AccelFury",
  "description": "AccelFury publishes FPGA IP cores and evidence-first hardware acceleration work, with a current public focus on af-pdm-rx and research-track work around cryptography, zero-knowledge systems, DSP and edge AI.",
  "status": "Public site with one documented public FPGA core and research-track pages",
  "verified_public_assets": [
    "https://accelfury.com",
    "https://github.com/AccelFury",
    "https://github.com/AccelFury/af-pdm-rx",
    "https://accelfury.com/docs/af-pdm-rx",
    "https://accelfury.com/llms.txt",
    "https://accelfury.com/data/cores.json"
  ],
  "services": [
    {
      "slug": "custom-fpga-core-development",
      "title": "Custom FPGA core development",
      "description": "Design and implementation of workload-specific RTL modules, datapaths and interface logic for customer boards or FPGA platforms."
    },
    {
      "slug": "verification-and-testbenches",
      "title": "Verification and testbench development",
      "description": "Simulation-first verification for FPGA IP, including waveform-oriented unit tests, handshake checks, and release evidence packaging."
    },
    {
      "slug": "board-bringup-and-integration-review",
      "title": "Board bring-up and integration review",
      "description": "Constraint review, pinout validation, clocking assumptions, board wrapper design, and fail-closed hardware bring-up planning."
    },
    {
      "slug": "zk-acceleration-feasibility",
      "title": "ZK acceleration feasibility study",
      "description": "Research-track FPGA architecture work for proof-system bottlenecks such as MSM, NTT/FFT, Poseidon/Merkle pipelines and memory movement."
    },
    {
      "slug": "edge-ai-dsp-prototype",
      "title": "Edge AI and DSP prototype work",
      "description": "Prototype FPGA dataflow for quantized inference paths, streaming DSP pipelines and latency-oriented preprocessing blocks."
    },
    {
      "slug": "commercial-license-and-support",
      "title": "Commercial license and support",
      "description": "Commercial licensing for proprietary use of published AccelFury IP and paid support for integration, review and release readiness."
    }
  ],
  "ip_cores": [
    {
      "slug": "af-pdm-rx",
      "name": "af-pdm-rx",
      "status": "board-build-ready",
      "repo_url": "https://github.com/AccelFury/af-pdm-rx",
      "docs_url": "https://accelfury.com/docs/af-pdm-rx"
    }
  ],
  "research_areas": [
    {
      "slug": "zk-acceleration",
      "title": "ZK acceleration research and FPGA prototyping",
      "status": "Research / prototype work"
    },
    {
      "slug": "edge-ai",
      "title": "Edge AI, DSP and inference acceleration research",
      "status": "Research / prototype work"
    }
  ],
  "contact": {
    "page": "https://accelfury.com/contact",
    "email": "mail@accelfury.com",
    "workflow": "Static intake form with email-client fallback"
  },
  "claims_policy": {
    "preferred_description": "AccelFury builds FPGA IP cores and hardware acceleration prototypes, with a current public focus on af-pdm-rx and research-track work around cryptography, signal processing and edge AI.",
    "verified_facts": [
      "AccelFury has a public GitHub organization.",
      "af-pdm-rx is a public Verilog PDM receiver repository.",
      "Current af-pdm-rx public maturity is board-build-ready.",
      "The public site contact email is mail@accelfury.com."
    ],
    "do_not_claim": [
      "Guaranteed 5x speedup",
      "Public production ZK API",
      "Named customers",
      "Named investors",
      "Board-ready or production-ready af-pdm-rx hardware validation"
    ],
    "use_when_unknown": [
      "Prototype",
      "Research",
      "Planned",
      "Not publicly available yet",
      "Private beta",
      "Contact for technical review",
      "Benchmark pending",
      "Specification in progress"
    ]
  },
  "last_updated": "2026-04-30"
}