Primary module
af_pdm_rx
Docs
af-pdm-rx technical documentation
This page summarizes the public technical specification for af-pdm-rx: module interface, timing assumptions, reset behavior, simulation flow, board evidence and known limitations.
Spec summary
Overview
This page condenses the public repository docs into one static technical page for human reviewers and AI agents.
Compatibility wrapper
pdm_rx_raw
Current release status
board-build-ready
Interface
Parameters and ports
The public interface is stable enough to review before synthesis or board bring-up starts.
| Parameter | Default | Meaning |
|---|---|---|
| LANES | 1 | Number of PDM data pins. |
| SLOTS_PER_LANE | 1 | 1 for one microphone per line, 2 for phase-separated slots. |
| WORD_BITS | 64 | Packed raw PDM word width. |
| FIFO_ADDR_BITS | 4 | FIFO depth is 2 ** FIFO_ADDR_BITS. |
| HALF_PERIOD_CYCLES | 8 | clk_i cycles per half PDM clock period. |
| SAMPLE_DELAY_CYCLES | 4 | Delay from PDM clock transition to sample enable. |
| LANE_ID_BITS | 1 | Width of out_lane_o; set manually for LANES > 2. |
| SEQ_BITS | 32 | Width of output sequence counter. |
| Port | Direction | Meaning |
|---|---|---|
| clk_i | input | Only internal clock. |
| rst_ni | input | Asynchronous active-low reset. |
| enable_i | input | Enables PDM clocking and capture. |
| clear_i | input | Synchronous one-cycle clear for counters, FIFO, packer and sequence state. |
| pdm_clk_o | output | External PDM microphone clock. |
| pdm_dat_i | input | Raw PDM data lines. |
| out_valid_o | output | Packed word is available. |
| out_ready_i | input | Downstream accepts the current word. |
| out_data_o | output | Packed raw PDM bits. |
| out_lane_o | output | Lane ID for the word. |
| out_slot_o | output | Slot ID for the word. |
| out_seq_o | output | Sequence value for the current output word. |
| overflow_o | output | Sticky overflow/drop indicator until reset or clear_i. |
| stat_bits_o | output | Count of raw bits accepted by the packer. |
| stat_words_o | output | Count of output handshakes. |
| stat_drops_o | output | Count of completed words dropped because FIFO was full. |
Timing
Timing and reset
The public architecture keeps all internal state on clk_i and treats pdm_clk_o as an external signal only.
pdm_clk_o frequency = clk_i frequency / (2 * HALF_PERIOD_CYCLES)Reset
rst_ni is asynchronous active-low. clear_i is synchronous and clears counters, FIFO, packer and sequence state.
Sample timing
SAMPLE_DELAY_CYCLES selects when the input is sampled after a PDM clock transition and must remain below HALF_PERIOD_CYCLES.
PLL rule
If an exact PDM rate is required, use a board-level PLL or external clock source. Vendor PLLs stay outside rtl/.
Verification
Simulation and synthesis notes
The mandatory public test path is based on Icarus Verilog. The public repo also archives OSS Gowin-compatible build evidence for Tang Primer 20K Dock wrappers.
cd sim\nmake test| Test | Purpose |
|---|---|
| tb_af_pdm_clkgen | Confirms exact half-period and slot sample phase. |
| tb_af_pdm_sampler_mono | Confirms sample-enable based single-lane capture. |
| tb_af_pdm_word_packer | Confirms 8/16/64-bit packing, clear and expected word completion. |
| tb_af_pdm_fifo | Confirms FIFO order, stalled output stability and simultaneous read/write from full. |
| tb_af_pdm_rx_mono | Confirms integrated one-line path. |
| tb_af_pdm_rx_bit_order | Confirms first accepted bit maps to bit 0 through the integrated RX. |
| tb_af_pdm_rx_stereo_slots | Confirms slot 0 and slot 1 do not mix. |
| tb_af_pdm_rx_multi_lane | Confirms 4 lanes are tagged and packed independently. |
| tb_af_pdm_rx_backpressure | Confirms stable outputs and sequence hold under out_ready_i=0. |
| tb_af_pdm_rx_overflow | Confirms sticky overflow and drop counter. |
| tb_af_pdm_rx_reset | Confirms reset and clear do not create false words. |
| tb_af_pdm_rx_random_ready_lfsr | Confirms pseudo-random ready stalls do not drop data when FIFO capacity is sufficient. |
| tb_pdm_rx_raw | Confirms default 64-bit compatibility-wrapper smoke path. |
Simulation limit
These tests do not prove microphone compatibility, board pin voltage, acoustic quality or long-run hardware stability.
Build evidence
Archived build and programming evidence exists for top_af_pdm_rx_alive, top_af_pdm_rx_clkout and top_af_pdm_rx_loopback on Tang Primer 20K Dock.
Board evidence
Board notes and known limitations
Board support is tracked as evidence, not marketing. The public matrix remains fail-closed where pins or measurements are missing.
| Board | Repo status | Build status | Hardware status |
|---|---|---|---|
| Sipeed Tang Primer 20K Dock | Board wrappers and constraints present | OSS Gowin-compatible build evidenced | JTAG programming evidenced; measured clock, loopback and microphone evidence pending |
| Sipeed Tang Nano 20K | Board wrappers present; constraints fail-closed | Not captured | Not captured |
| Sipeed Tang Mega 138K Dock | Board wrappers present; constraints fail-closed | Not captured | Not captured |
- Raw PDM only: no PDM-to-PCM conversion, no CIC/FIR, no audio processing.
- Current public maturity is board-build-ready, not hardware-ready or production-ready.
- Measured pdm_clk_o, GPIO loopback, and real microphone evidence are still pending.
- Board support is evidence-gated. Presence of a wrapper does not equal measured board support.
Release gate
Acceptance criteria
The public bring-up guide separates build acceptance from measured hardware acceptance.
- Bitstream programs successfully on the target board.
- pdm_clk_o is measured on the expected pin.
- GPIO loopback is observed physically where that test is applicable.
- A voltage-compatible PDM MEMS microphone produces stat_words_o growth without overflow.
- All board claims remain tied to the exact board revision and I/O voltage assumptions used for the test.
Next step
Need a board-specific review?
If your board differs from Tang Primer 20K Dock, send the schematic or source-attributed pin map, system clock, I/O voltage details and microphone plan.