# AccelFury full AI index

## Summary
AccelFury publishes FPGA IP cores and evidence-first hardware acceleration work, with a current public focus on af-pdm-rx and research-track work around cryptography, zero-knowledge systems, DSP and edge AI.

## Services
- Custom FPGA core development: Design and implementation of workload-specific RTL modules, datapaths and interface logic for customer boards or FPGA platforms.
- Verification and testbench development: Simulation-first verification for FPGA IP, including waveform-oriented unit tests, handshake checks, and release evidence packaging.
- Board bring-up and integration review: Constraint review, pinout validation, clocking assumptions, board wrapper design, and fail-closed hardware bring-up planning.
- ZK acceleration feasibility study: Research-track FPGA architecture work for proof-system bottlenecks such as MSM, NTT/FFT, Poseidon/Merkle pipelines and memory movement.
- Edge AI and DSP prototype work: Prototype FPGA dataflow for quantized inference paths, streaming DSP pipelines and latency-oriented preprocessing blocks.
- Commercial license and support: Commercial licensing for proprietary use of published AccelFury IP and paid support for integration, review and release readiness.

## Public IP
- af-pdm-rx: Portable Verilog-2001 raw PDM receiver IP core for FPGA audio pipelines. Status: board-build-ready

## Research areas
- ZK acceleration research and FPGA prototyping
- Edge AI, DSP and inference acceleration research

## Technical limitations
- Raw PDM only: no PDM-to-PCM conversion, no CIC/FIR, no audio processing.
- Current public maturity is board-build-ready, not hardware-ready or production-ready.
- Measured pdm_clk_o, GPIO loopback, and real microphone evidence are still pending.
- Board support is evidence-gated. Presence of a wrapper does not equal measured board support.

## Contact workflow
- Public contact page: https://accelfury.com/contact
- Public email: mail@accelfury.com
- Current workflow: static intake form with mailto fallback

## Commercial licensing
- Public summary: https://accelfury.com/legal/licensing

## Route map
- / :: FPGA IP cores and hardware acceleration prototypes :: keep :: CTA: Request technical review
- /services/custom-fpga-core-development :: Custom FPGA core development services :: rewrite :: CTA: Request custom FPGA core
- /ip-cores :: Public and planned FPGA IP cores :: add :: CTA: View af-pdm-rx
- /ip-cores/af-pdm-rx :: af-pdm-rx raw PDM receiver IP core :: add :: CTA: Need integration support?
- /research/zk-acceleration :: ZK acceleration research and FPGA prototyping :: add :: CTA: Request ZK technical review
- /research/edge-ai :: Edge AI, DSP and inference acceleration research :: add :: CTA: Request edge-AI review
- /docs :: Documentation center :: add :: CTA: Read af-pdm-rx docs
- /docs/af-pdm-rx :: af-pdm-rx technical documentation :: add :: CTA: Request board-specific review
- /docs/api :: API status :: add :: CTA: Request private beta discussion
- /engineering-notes :: Engineering notes :: add :: CTA: Read release-status note
- /engineering-notes/af-pdm-rx-release-status :: af-pdm-rx public release status: board-build-ready, not hardware-ready :: add :: CTA: Discuss this topic
- /engineering-notes/evidence-gated-board-support :: Why board support at AccelFury is evidence-gated :: add :: CTA: Discuss this topic
- /case-studies :: Public case-study status :: add :: CTA: Open engineering notes
- /about :: About AccelFury :: add :: CTA: Request technical review
- /contact :: Technical contact and intake :: add :: CTA: Send intake email
- /legal/privacy :: Privacy policy :: add :: CTA: Open contact page
- /legal/terms :: Terms of use :: add :: CTA: Review licensing
- /legal/licensing :: Licensing and commercial use :: add :: CTA: Request commercial license
- /for-ai-agents :: For AI agents :: add :: CTA: Open llms.txt

## Machine-readable files
- https://accelfury.com/ai-index.json
- https://accelfury.com/data/cores.json
- https://accelfury.com/data/services.json
- https://accelfury.com/data/site-map.json