IP core

af-pdm-rx: Portable Verilog-2001 raw PDM receiver IP core for FPGA audio pipelines.

af-pdm-rx generates a microphone clock, samples one or more raw 1-bit PDM input lanes, packs accepted bits into fixed-width words and exposes a valid/ready stream for downstream FPGA logic.

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Core facts

Behavior

What the core does and explicitly does not do.

Does: Generates a PDM microphone clock.
Samples one or more raw PDM data lanes.
Packs raw PDM bits into fixed-width words.
Emits words through a valid/ready stream.
Does not: Does not convert PDM to PCM.
Does not include CIC, FIR or audio filtering.
Does not publish a hardware-ready or production-ready claim.
Typical use cases: Raw microphone capture experiments.
FPGA audio front-end prototypes.
Integration test source for streaming and backpressure paths.

Spec

Interface

Ports, parameters, clocks and reset behavior are shown in contained tables for desktop and mobile review.

Parameter	Default	Meaning
LANES	1	Number of PDM data pins.
SLOTS_PER_LANE	1	One microphone per line or phase-separated slots.
WORD_BITS	64	Packed raw PDM word width.
FIFO_ADDR_BITS	4	FIFO depth is 2 ** FIFO_ADDR_BITS.
HALF_PERIOD_CYCLES	8	clk_i cycles per half PDM clock period.
SAMPLE_DELAY_CYCLES	4	Delay from PDM clock transition to sample enable.
LANE_ID_BITS	1	Width of out_lane_o; set manually for LANES > 2.
SEQ_BITS	32	Width of output sequence counter.

Port	Direction	Meaning
clk_i	input	Only internal logic clock.
rst_ni	input	Asynchronous active-low reset.
enable_i	input	Enables PDM clocking and capture.
clear_i	input	Synchronous one-cycle clear for counters, FIFO, packer and sequence state.
pdm_clk_o	output	External PDM microphone clock.
pdm_dat_i	input	Raw PDM data lines.
out_valid_o	output	Packed word is available.
out_ready_i	input	Downstream accepts the current word.
out_data_o	output	Packed raw PDM bits.
out_lane_o	output	Lane ID for the word.
out_slot_o	output	Slot ID for the word.
out_seq_o	output	Sequence value for the current output word.
overflow_o	output	Sticky overflow/drop indicator until reset or clear_i.
stat_bits_o	output	Count of raw bits accepted by the packer.
stat_words_o	output	Count of output handshakes.
stat_drops_o	output	Count of completed words dropped because FIFO was full.

Interface	Type	Direction	Signals	Description
valid_ready_stream	valid/ready	output	out_valid_o, out_ready_i, out_data_o, out_lane_o, out_slot_o, out_seq_o	Packed raw PDM words are emitted over a stable valid/ready stream.
pdm_microphone	PDM	external	pdm_clk_o, pdm_dat_i	External microphone clock output and one or more raw PDM data inputs.
control_status	simple wires	mixed	enable_i, clear_i, overflow_o, stat_bits_o, stat_words_o, stat_drops_o	Control and status wires for enable, synchronous clear, overflow and counters.

Clock	Role	Notes
clk_i	single internal clock domain	All internal state is clocked by clk_i.
pdm_clk_o	external microphone clock output	pdm_clk_o is generated for the microphone and is not used as an internal logic clock.

Reset	Polarity	Type	Notes
rst_ni	active-low	asynchronous	Primary reset for all state.
clear_i	active-high	synchronous one-cycle clear	Clears counters, FIFO, packer and sequence state.

Integration notes

Integration

Board-local wrappers, constraints and PLL choices are kept separate from reusable RTL.

af_pdm_rx #(
  .LANES(1),
  .SLOTS_PER_LANE(1),
  .WORD_BITS(64),
  .FIFO_ADDR_BITS(4)
) u_af_pdm_rx (
  .clk_i(clk_i),
  .rst_ni(rst_ni),
  .enable_i(enable_i),
  .clear_i(clear_i),
  .pdm_clk_o(pdm_clk_o),
  .pdm_dat_i(pdm_dat_i),
  .out_valid_o(out_valid_o),
  .out_ready_i(out_ready_i),
  .out_data_o(out_data_o)
);

Top-level wrapper

af_pdm_rx

Connection notes

Connect clk_i, rst_ni, enable_i, clear_i, PDM pins and downstream valid/ready signals. Keep board-local PLLs and constraints outside the reusable RTL core.

Timing assumptions

pdm_clk_o frequency = clk_i frequency / (2 * HALF_PERIOD_CYCLES). Use a board-level PLL or external clock selection when an exact PDM rate is required.

Clock domains

Single internal clk_i domain. pdm_clk_o is an external output and not an internal clock.

Board constraints

Board constraints are evidence-gated. A wrapper does not imply measured hardware support.

Evidence

Verification

Verification and board evidence are tracked as separate gates.

Simulation status

13 Icarus Verilog test targets are documented as passing.

Testbench status

Public testbenches cover clock generation, sampling, packing, FIFO behavior, slots, lanes, backpressure, overflow, reset and randomized ready stalls.

Formal checks

Formal checks are not published.

Board validation

Tang Primer 20K Dock build and JTAG programming evidence are public. Measured PDM clock, GPIO loopback and microphone evidence remain pending.

Known gaps

Open verification gaps are listed explicitly.

No public real microphone capture yet.
No public long-run hardware validation yet.
No public fmax/resource table committed as measured data yet.

Do not infer beyond this

Limitations

Known limitations are part of the public core contract.

Raw PDM only: no PDM-to-PCM conversion, no CIC/FIR and no audio processing.
Current public release label is board-build-ready, not hardware-ready or production-ready.
Measured pdm_clk_o, GPIO loopback and real microphone evidence are still pending.
Board support is evidence-gated. Presence of a wrapper does not equal measured board support.

Next step

Need support or a commercial license?

Send the board, clock source, I/O voltage assumptions, downstream interface, verification target and license scope.

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