Deliverables
Typical outputs for this service.
- spec
- RTL
- testbench
- docs
- integration wrapper
- simulation report
- optional board validation
Service
Custom FPGA IP development
Specification, RTL implementation, verification and integration support for workload-specific FPGA/IP cores.
Scope
Deliverables
Scope is defined as reviewable engineering output.
Inputs required
Useful information for an initial review.
- Workload description
- Target FPGA or exact board
- Clocking and interface constraints
- Latency, throughput and power goals
- Verification and delivery requirements
Limitations
Boundaries that prevent unsupported claims.
- Performance guarantees depend on the exact workload, FPGA family and board constraints.
- Public benchmark numbers are not claimed until reproducible measurements are available.
Process
Engagement flow
The same review flow applies to public IP support, private prototypes and custom RTL work.
- Intake: workload, target, constraints and NDA requirement.
- Feasibility: architecture options, risks and evidence gaps.
- Implementation: RTL, wrappers, tests and docs where scope is approved.
- Review: simulation, build or measurement evidence before public claims.
Trust
Evidence and licensing references
Current public proof is intentionally limited to what can be inspected.
Public proof style
af-pdm-rx demonstrates the preferred public pattern: portable RTL, tests, docs, board wrappers and explicit evidence gaps.
Licensing boundary
Commercial and proprietary use is handled by direct agreement where applicable.
Next step
Request Custom FPGA IP
Send the workload, target board or FPGA family, timing target, throughput goal, power constraints, interface assumptions and NDA requirement.