IP component

af-pdm-rx

af-pdm-rx generates a microphone clock, samples one or more raw 1-bit PDM input lanes, packs accepted bits into fixed-width words and exposes a valid/ready stream for downstream FPGA logic.

Discuss availability Read specifications

Stage: Prototype
Access: Availability unconfirmed

Raw PDM only: no PDM-to-PCM conversion, no CIC/FIR and no audio processing.

Simulation results are reported; functional board measurements are unconfirmed.

Signal path

Raw PDMMicrophone clock and 1-bit inputs
Capture & packClock, sample and buffer
Raw wordsvalid/ready output

Specifications

Parameter	Default	Meaning
LANES	1	Number of PDM data pins.
SLOTS_PER_LANE	1	One microphone per line or phase-separated slots.
WORD_BITS	64	Packed raw PDM word width.
FIFO_ADDR_BITS	4	FIFO depth is 2 ** FIFO_ADDR_BITS.
HALF_PERIOD_CYCLES	8	clk_i cycles per half PDM clock period.
SAMPLE_DELAY_CYCLES	4	Delay from PDM clock transition to sample enable.
LANE_ID_BITS	1	Width of out_lane_o; set manually for LANES > 2.
SEQ_BITS	32	Width of output sequence counter.

Port	Direction	Meaning
clk_i	input	Only internal logic clock.
rst_ni	input	Asynchronous active-low reset.
enable_i	input	Enables PDM clocking and capture.
clear_i	input	Synchronous one-cycle clear for counters, FIFO, packer and sequence state.
pdm_clk_o	output	External PDM microphone clock.
pdm_dat_i	input	Raw PDM data lines.
out_valid_o	output	Packed word is available.
out_ready_i	input	Downstream accepts the current word.
out_data_o	output	Packed raw PDM bits.
out_lane_o	output	Lane ID for the word.
out_slot_o	output	Slot ID for the word.
out_seq_o	output	Sequence value for the current output word.
overflow_o	output	Sticky overflow/drop indicator until reset or clear_i.
stat_bits_o	output	Count of raw bits accepted by the packer.
stat_words_o	output	Count of output handshakes.
stat_drops_o	output	Count of completed words dropped because FIFO was full.

Interface	Type	Direction	Signals	Description
valid_ready_stream	valid/ready	output	out_valid_o, out_ready_i, out_data_o, out_lane_o, out_slot_o, out_seq_o	Packed raw PDM words are emitted over a stable valid/ready stream.
pdm_microphone	PDM	external	pdm_clk_o, pdm_dat_i	External microphone clock output and one or more raw PDM data inputs.
control_status	simple wires	mixed	enable_i, clear_i, overflow_o, stat_bits_o, stat_words_o, stat_drops_o	Control and status wires for enable, synchronous clear, overflow and counters.

Clock	Role	Notes
clk_i	single internal clock domain	All internal state is clocked by clk_i.
pdm_clk_o	external microphone clock output	pdm_clk_o is generated for the microphone and is not used as an internal logic clock.

Reset	Polarity	Type	Notes
rst_ni	active-low	asynchronous	Primary reset for all state.
clear_i	active-high	synchronous one-cycle clear	Clears counters, FIFO, packer and sequence state.

Verification

Based on the site record dated 2026-05-01. Component revision, test configuration and primary reports are unconfirmed; these results have not been independently repeated.

Check	Result
simulation	Reported simulation result
synthesis	Synthesis: unknown
implementation	Reported implementation result
programming	Reported programming result
hardware functional	Hardware functional: unknown
formal	Formal: unknown
application acceptance	Application acceptance: unknown

Primary review: Report and component revision unconfirmed.

The source summary reports 13 Icarus test targets and selected Tang Primer 20K Dock builds and JTAG programming. It is not a primary test report. Read the source summary

Resource usage, fmax and power measurements are not available.

Integration

Keep board-specific clocks and constraints outside the reusable logic.

af_pdm_rx #(
  .LANES(1),
  .SLOTS_PER_LANE(1),
  .WORD_BITS(64),
  .FIFO_ADDR_BITS(4)
) u_af_pdm_rx (
  .clk_i(clk_i),
  .rst_ni(rst_ni),
  .enable_i(enable_i),
  .clear_i(clear_i),
  .pdm_clk_o(pdm_clk_o),
  .pdm_dat_i(pdm_dat_i),
  .out_valid_o(out_valid_o),
  .out_ready_i(out_ready_i),
  .out_data_o(out_data_o)
);

Connections

Connect clk_i, rst_ni, enable_i, clear_i, PDM pins and downstream valid/ready signals. Keep board-local PLLs and constraints outside the reusable RTL core.

Clocking

pdm_clk_o frequency = clk_i frequency / (2 * HALF_PERIOD_CYCLES). Use a board-level PLL or external clock selection when an exact PDM rate is required.

Board	Family	Status	Notes
Sipeed Tang Primer 20K Dock	Gowin GW2A	reported build	Reported wrapper, build and JTAG programming. Functional PDM measurements unconfirmed.
Sipeed Tang Nano 20K	Gowin GW2AR	wrapper only	Reported wrapper only. Constraints and functional measurements unconfirmed.
Sipeed Tang Mega 138K Dock	Gowin GW5A	wrapper only	Reported wrapper only. Constraints and functional measurements unconfirmed.

Toolchain	Status	Notes
Icarus Verilog	reported simulation	Icarus Verilog / vvp simulation path; source summary only.
OSS CAD Suite / Gowin-compatible flow	reported build	Selected Tang Primer 20K Dock builds; component revision unconfirmed.

Limitations

The earlier board-build-ready label does not establish functional hardware qualification.
Measured PDM clock, GPIO loopback and microphone results are unconfirmed.
A board wrapper does not establish functional hardware support.

Licensing

AccelFury Source Available License v1.0. Closed-source or proprietary use requires a separate commercial license.

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