IP core catalog

FPGA IP core catalog

Find a component and review its interfaces, limitations and verification results.

IP components

Audio & signal processing

Prototype

Verilog-2001 raw PDM receiver IP core for FPGA audio pipelines.

Raw PDM only: no PDM-to-PCM conversion, no CIC/FIR and no audio processing.

Access: Availability unconfirmed
Verification: Reported simulation result
License: AccelFury Source Available License v1.0. Closed-source or proprietary use requires a separate commercial license.

Describe the function, interfaces and target you have in mind.