IP cores
1 true IP core documented in /data/cores.json.
About
Portable FPGA IP cores, an open Rust toolchain (af) and evidence-first hardware acceleration work. Every public claim is backed by a repo, test or measurement.
Public surface
4 public repositories at https://github.com/AccelFury: 1 true IP core, 1 toolchain, 1 template repository, plus the org profile.
1 true IP core documented in /data/cores.json.
af — Rust CLI for manifests, simulation, lint and packaging.
core-template is a starter repository and example surface, not a catalog core.
0 GitHub releases. Reviewable evidence lives in the repos.
Repository templates
Templates are listed separately so the IP catalog stays reserved for reusable cores.
Production-style FPGA IP repository template with af_mod_add modular-addition example, registries, checks and board metadata.
Tooling
The same toolchain powers all AccelFury IP — it is the most active artifact of the organization.
Rust CLI for FPGA IP development: manifests, Verilator simulation, Yosys checks, FuseSoC packaging, vendor backend orchestration.
Principles
Claims on this site must be backed by repo-visible docs, tests, release notes or hardware evidence.
Boundary
The site avoids customer, investor, API and catalog claims that are not public.