Research / prototyping

Edge AI / DSP pipeline prototyping

Evaluate FPGA data paths for sensor preprocessing, streaming DSP and selected inference operators.

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Scope

Evaluate an operator set or DSP chain against precision, bandwidth and board constraints.

Deliverables

  • dataflow design
  • quantization assumptions
  • latency estimate
  • target board constraints
  • prototype RTL/HLS plan

Inputs

  • Model, operator set or DSP chain
  • Precision and quantization assumptions
  • Input/output bandwidth
  • Target board or device family

Acceptance and exclusions

The deliverable records the dataflow, quantization assumptions, latency estimate and target constraints. Prototype RTL requires a separate agreed scope.

  • A complete inference appliance and model-to-NPU compiler are outside this service.
  • Power and throughput depend on board power delivery, memory topology and the exact operator mix.

Delivery, licensing and support terms are agreed for the project. How we work.